Title:
【発明の名称】高信頼度化情報処理装置
Document Type and Number:
Japanese Patent JP3063334
Kind Code:
B2
Abstract:
A highly reliable information processor system of the present invention takes in the bus cycle start signals which are output to notify outside devices of the timings where the first to third microprocessors start their bus cycles so as to compare them with each other and, detects any malfunction of a microprocessor based on discrepancy in start timing among bus cycles. When it judges that the first microprocessor in execution mode malfunctions, it logically isolates the first microprocessor operating in execution mode and causes either of the second or third microprocessors operating in monitor mode to enter execution mode. After such degradation from triple-processor configuration to double-processor configuration, it executes again the bus cycle which has been executed at the time of malfunction detection.
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Inventors:
Kazuhide Hosaka
Application Number:
JP33669691A
Publication Date:
July 12, 2000
Filing Date:
December 19, 1991
Export Citation:
Assignee:
NEC
International Classes:
G06F11/18; G06F15/16; G06F15/177; (IPC1-7): G06F11/18; G06F15/177
Domestic Patent References:
| JP633344A | ||||
| JP56123042A | ||||
| JP635439A | ||||
| JP329033A | ||||
| JP219943A | ||||
| JP52131438A | ||||
| JP340036A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)