Title:
LAYOUT DESIGN METHOD AND LAYOUT DESIGN APPARATUS OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2017068779
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To eliminate clock buffers excessively inserted by clock tree synthesis (CTS) and to reduce power consumption of a semiconductor device.SOLUTION: A layout design method includes selecting, from a clock tree obtained by CTS: a clock line that has a fanout of a prescribed value or less, includes a clock buffer in the middle, and has a total wiring length of a prescribed length or more; and a clock line in which the degree of density of arranged flip flops as supply destination of clock is a prescribed degree or more, and inter-clock skew given to each flip flop is a prescribed value or less. The method further includes considering a possibility of eliminating or reducing the size of the clock buffer interposed in the selected clock line.SELECTED DRAWING: Figure 1
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Inventors:
ANDO HIROYUKI
SUGISAKI HIROKI
HATA NAOHIRO
KOIDE YUI
TERAUCHI YOSHIHIKO
YAMAUCHI MANABU
SATO KAZUICHI
SUGISAKI HIROKI
HATA NAOHIRO
KOIDE YUI
TERAUCHI YOSHIHIKO
YAMAUCHI MANABU
SATO KAZUICHI
Application Number:
JP2015196572A
Publication Date:
April 06, 2017
Filing Date:
October 02, 2015
Export Citation:
Assignee:
TOPPAN PRINTING CO LTD
International Classes:
G06F17/50; H01L21/82; H01L21/822; H01L27/04
Attorney, Agent or Firm:
Takashi Matsumoto
Naoya Goto
Naoya Goto