Title:
Level shift circuits, integrated circuits, and power semiconductor modules
Document Type and Number:
Japanese Patent JP6289673
Kind Code:
B2
Abstract:
A primary circuit outputs, in response to an input signal, a first signal with a first reference potential. A level shift main circuit converts the reference potential of the first signal received from the primary circuit to a second reference potential to output a second signal with the second reference potential. A secondary circuit generates an output signal with the second reference potential using the second signal. At least one rectifying element circuit is provided between the primary circuit and the secondary circuit. At least one of the primary circuit and the secondary circuit includes at least one detection circuit detecting a change in a current flowing through the rectifying element circuit to determine whether a potential corresponding to the second reference potential is lower than or equal to a potential corresponding to the first reference potential.
Inventors:
Kazuya Gaizono
Akio Yamamoto
Wang Dong
Akio Yamamoto
Wang Dong
Application Number:
JP2016564506A
Publication Date:
March 07, 2018
Filing Date:
December 17, 2014
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
H03K19/00; H02M1/08
Domestic Patent References:
| JP2012186838A | ||||
| JP200333040A | ||||
| JP2011259360A | ||||
| JP20076048A | ||||
| JP201167029A | ||||
| JP200092824A | ||||
| JP2006211760A | ||||
| JP2010263116A |
Foreign References:
| US20110074485 |
Attorney, Agent or Firm:
Yoshitake Hidetoshi
Takahiro Arita
Takahiro Arita
Previous Patent: A synthetic-aperture-radar signal processor and a synthetic-aperture-radar signal-processing program
Next Patent: COPYING DEVICE
Next Patent: COPYING DEVICE