Title:
低ドロップアウトレギュレータ
Document Type and Number:
Japanese Patent JP7165667
Kind Code:
B2
Abstract:
A low-dropout regulator comprises a first switching transistor, a comparator, and a Miller capacitor. The first terminal of the first switching transistor is connected to a load, and the second terminal of the first switching transistor is connected to a power supply voltage. The first input terminal of the comparator is connected to a reference voltage, the second input terminal of the comparator is connected to the first terminal of the first switching transistor, and the output terminal of the comparator is connected to the control terminal of the first switching transistor. The first terminal of the Miller capacitor is connected to the control terminal of the first switching transistor, and the second terminal of the Miller capacitor is connected to the first terminal of the first switching transistor and the load.
Inventors:
Pan Feng
Le Zenyu
Jan Steve Wei
Yang Simon Si-Nin
Le Zenyu
Jan Steve Wei
Yang Simon Si-Nin
Application Number:
JP2019548933A
Publication Date:
November 04, 2022
Filing Date:
March 01, 2018
Export Citation:
Assignee:
Yangtze Memory Technologies Co.,Ltd.
International Classes:
H02M3/155; G05F1/56
Domestic Patent References:
| JP3063805A | ||||
| JP2013250728A | ||||
| JP2002280889A |
Foreign References:
| US20110156674 |
Attorney, Agent or Firm:
Hiroi Arai
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