Title:
A macro pin hybrid interconnection array and a manufacturing method for the same
Document Type and Number:
Japanese Patent JP5906022
Kind Code:
B2
Abstract:
A micro pin interconnect array (10,30,40) includes a crystal anode array (18) and a ceramic substrate (14). The array (18) and substrate (14) are joined together using interconnect (12,32,42) geometry having a large aspect ratio of height to width, the interconnects (12,32,42) being copper pillars, gold stud bumps or gold plated pillars. The joint affixing the interconnect (12,32,42) to the crystal anode array (18) is devoid of solder. The structure minimises coefficient of thermal expansion (CTE) mismatches between the crystal (18) (cadmium zinc telluride (CZT), cadmium telluride (CdTe)) and the substrate (14), offering low local strain.
Inventors:
Charles Gerrard Woichk
John Eric Tokachik
Brian David Janov
Tan Tsang
John Eric Tokachik
Brian David Janov
Tan Tsang
Application Number:
JP2011088708A
Publication Date:
April 20, 2016
Filing Date:
April 13, 2011
Export Citation:
Assignee:
GENERAL ELECTRIC COMPANY
International Classes:
H01L21/60; H01L23/50
Domestic Patent References:
| JP2004048012A | ||||
| JP11017309A | ||||
| JP2001102481A | ||||
| JP200781380A | ||||
| JP2007214191A | ||||
| JP200981153A | ||||
| JP2010521587A |
Foreign References:
| US20070131868 |
Attorney, Agent or Firm:
Arakawa Satoshi
Hirokazu Ogura
Toshihisa Kurokawa
Hirokazu Ogura
Toshihisa Kurokawa
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