Title:
回路装置の製造方法
Document Type and Number:
Japanese Patent JP4761662
Kind Code:
B2
Abstract:
In a step of covering a rear face resist, by recognizing position of a positioning mark exposed at a rear face of a conductive foil, position recognition of a conductive pattern of the rear face of every block or every conductive foil is performed indirectly, and a resist layer is formed except an opening portion forming the scheduled rear face electrode on the conductive pattern. Therefore, a method of manufacturing a circuit device shortened in time.
Inventors:
Yoshiyuki Kobayashi
Noriaki Sakamoto
Koji Takahashi
Noriaki Sakamoto
Koji Takahashi
Application Number:
JP2001216245A
Publication Date:
August 31, 2011
Filing Date:
July 17, 2001
Export Citation:
Assignee:
Sanyo Electric Co., Ltd.
International Classes:
H01L23/12; H01L21/48; H01L23/31; H05K1/00; H01L23/544; H05K3/20; H05K3/28
Domestic Patent References:
| JP11195733A | ||||
| JP2000150760A | ||||
| JP9260560A | ||||
| JP10247715A | ||||
| JP2001028420A | ||||
| JP2001339049A | ||||
| JP11087488A |
Foreign References:
| WO1995026047A1 |
Attorney, Agent or Firm:
Takashi Okada
Katsuhiko Sudo
Katsuhiko Sudo