Title:
SEMICONDUCTOR DEVICE MANUFACTURING METHOD, WAFER WITH SEMICONDUCTOR ELEMENT LAMINATE, SEMICONDUCTOR ELEMENT LAMINATE AND SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2016082018
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which achieves excellent workability and excellent connectivity even when a thinned wafer is used.SOLUTION: A semiconductor device manufacturing method comprises: a resin composition layer formation process (S2) of forming a resin composition layer on a surface of a first semiconductor wafer which is fixed to a support medium and has a conductor, in which the surface is on the side opposite to the support medium; a conductor exposure process (S3) of performing exposure and developing on the resin composition layer to expose the conductor; an adhesive tape attachment process (S4) of attaching an adhesive tape on the surface of the first semiconductor wafer on the side opposite to the support medium; a support medium separation process (S5) of separating the support medium from the first semiconductor wafer; a dicing process (S6) of dicing the first semiconductor wafer to obtain semiconductor chips with resin composition; an adhesive tape separation process (S7) of separating the semiconductor chips with resin composition from the adhesive tape; and a connection process (S8) of connecting the semiconductor chips with resin composition to a connection member for connecting the semiconductor chips with resin composition.SELECTED DRAWING: Figure 1
Inventors:
MITSUKURA KAZUYUKI
ZEISHO RYOTA
RAI HANAKO
MINEGISHI TOMONORI
ZEISHO RYOTA
RAI HANAKO
MINEGISHI TOMONORI
Application Number:
JP2014210662A
Publication Date:
May 16, 2016
Filing Date:
October 15, 2014
Export Citation:
Assignee:
HITACHI CHEMICAL CO LTD
International Classes:
H01L21/60; H01L21/301; H01L25/065; H01L25/07; H01L25/18
Attorney, Agent or Firm:
Yoshiki Hasegawa
Yoshinori Shimizu
Tomoya Furoshita
Osaka Koichi
Yoshinori Shimizu
Tomoya Furoshita
Osaka Koichi