Title:
A manufacturing method of a semiconductor device
Document Type and Number:
Japanese Patent JP5938118
Kind Code:
B2
Abstract:
A manufacturing method of a semiconductor device, which includes the steps of forming a gate electrode layer over a substrate having an insulating surface, forming a gate insulating layer over the gate electrode layer, forming an oxide semiconductor layer over the gate insulating layer, forming a source electrode layer and a drain electrode layer over the oxide semiconductor layer, forming an insulating layer including oxygen over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and after formation of an insulating layer including hydrogen over the insulating layer including oxygen, performing heat treatment so that hydrogen in the insulating layer including hydrogen is supplied to at least the oxide semiconductor layer.
Inventors:
Shunpei Yamazaki
Application Number:
JP2015080053A
Publication Date:
June 22, 2016
Filing Date:
April 09, 2015
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H01L21/336; G02F1/1368; H01L21/477; H01L29/786; H01L51/50; H05B44/00
Domestic Patent References:
| JP2008281988A | ||||
| JP2011139054A | ||||
| JP2007123861A |
Foreign References:
| US20100084648 | ||||
| WO2010047077A1 | ||||
| US20110133191 | ||||
| US20070072439 |