Title:
A manufacturing method of a semiconductor device and a semiconductor device
Document Type and Number:
Japanese Patent JP6208971
Kind Code:
B2
Abstract:
A semiconductor device has a p-type metal oxide semiconductor layer; a source electrode connected with the p-type metal oxide semiconductor layer; a drain electrode connected with the p-type metal oxide semiconductor layer; and a gate electrode arranged to oppose to a part of the p-type metal oxide semiconductor layer. The gate electrode and the drain electrode are separated from each other in a top view.
Inventors:
Jun Sunamura
Takaaki Kaneko
Naoya Kobu
Shinobu Saito
Yoshihiro Hayashi
Takaaki Kaneko
Naoya Kobu
Shinobu Saito
Yoshihiro Hayashi
Application Number:
JP2013082747A
Publication Date:
October 04, 2017
Filing Date:
April 11, 2013
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H01L29/786; H01L21/28; H01L21/336; H01L27/088; H01L29/417
Domestic Patent References:
| JP2012160679A | ||||
| JP2012169605A | ||||
| JP2010212285A | ||||
| JP2012028731A | ||||
| JP2011258940A | ||||
| JP2011216574A |
Foreign References:
| US20110309353 | ||||
| WO2011093506A1 | ||||
| WO2012121255A1 |
Attorney, Agent or Firm:
Minoru Kudo
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