Title:
MEMORY DEVICE
Document Type and Number:
Japanese Patent JP2022118984
Kind Code:
A
Abstract:
To provide a memory device that prevents a chip size from being rate-limited to the size of a peripheral circuit.SOLUTION: A memory device comprises a first chip, and a second chip that is provided on the first chip. The first chip includes a first substrate, a first electrode, and a first memory cell array that is provided between the first substrate and the first electrode. The second chip includes a second substrate, a second electrode that is brought into contact with the first electrode, and a second memory cell array that is provided between the second substrate and the second electrode.SELECTED DRAWING: Figure 3
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Inventors:
TAKEKIDA HIDEHITO
Application Number:
JP2021015875A
Publication Date:
August 16, 2022
Filing Date:
February 03, 2021
Export Citation:
Assignee:
KIOXIA CORP
International Classes:
H01L27/11582; H01L21/02; H01L21/336
Attorney, Agent or Firm:
Masatoshi Kurata
Nobuhisa Nogawa
Ryuji Mine
Naoki Kono
Sanae Kaneko
Nobuhisa Nogawa
Ryuji Mine
Naoki Kono
Sanae Kaneko