Title:
Memory management unit for direct access to the system interface
Document Type and Number:
Japanese Patent JP6305905
Kind Code:
B2
Abstract:
A memory management unit (MMU) for servicing transaction requests from one or more processor threads is described. The MMU can include a translation lookaside buffer (TLB). The TLB can include a storage module and a logic circuit. The storage module can store a bit indicating one of a plurality of interfaces. The bit can be associated with a physical address range. The logic circuit can route a physical address within the physical address range to the one of the plurality of interfaces.
Inventors:
Ajay Anant Ingle
Christopher Edward Coob
Christopher Edward Coob
Application Number:
JP2014230935A
Publication Date:
April 04, 2018
Filing Date:
November 13, 2014
Export Citation:
Assignee:
QUALCOMM INCORPORATED
International Classes:
G06F12/10
Other References:
米国特許第6912644号明細書
米国特許出願公開第2007/0050594号明細書
特開2003-281079号公報
特開昭63-188251号公報
特開平10-91526号公報
特開2004-288155号公報
特許第5680533号公報
米国特許出願公開第2007/0050594号明細書
特開2003-281079号公報
特開昭63-188251号公報
特開平10-91526号公報
特開2004-288155号公報
特許第5680533号公報
Attorney, Agent or Firm:
Kurata Masatoshi
Yoshihiro Fukuhara
Morisezo Iseki
Takashi Okada
Yoshihiro Fukuhara
Morisezo Iseki
Takashi Okada