Title:
A memory which has a latching sense amplifier which has tolerance in negative bias temperature instability, and a related method
Document Type and Number:
Japanese Patent JP5988348
Kind Code:
B2
Abstract:
An integrated circuit includes a memory cell and a sense amplifier coupled to the memory cell via a first bit line and a second bit line. The sense amplifier includes first and second inverters cross-coupled to provide a latch. The first inverter is responsive to a first data signal provided by the memory cell over the first bit line. The second inverter is responsive to a second data signal as provided by the memory cell over the second bit line. A first negative bias temperature instability (NBTI) compensation transistor includes a source electrode coupled to receive a reference voltage, a drain electrode coupled to a source electrode of the first inverter, and a gate electrode coupled to first logic responsive to the first data signal. A second NBTI compensation transistor includes a source electrode coupled to receive the reference voltage, a drain electrode coupled to a source electrode of the second inverter, and a gate electrode coupled to second logic responsive to the second data signal, wherein the second data signal is a logical complement of the first data signal.
Inventors:
Alexander B. Hoffler
James Di. Barnet
Scott Eye Remington
James Di. Barnet
Scott Eye Remington
Application Number:
JP2011272993A
Publication Date:
September 07, 2016
Filing Date:
December 14, 2011
Export Citation:
Assignee:
Freescale Semiconductor, Inc.
International Classes:
G11C17/00; G11C17/14
Domestic Patent References:
| JP2011134374A | ||||
| JP2012064292A | ||||
| JP2011048870A | ||||
| JP2010015614A | ||||
| JP2011518402A |
Attorney, Agent or Firm:
Atsushi Honda
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