Title:
【発明の名称】小さい位相差の測定のための方法および回路装置
Document Type and Number:
Japanese Patent JP3187081
Kind Code:
B2
Abstract:
For measuring a phase difference ( phi ) between an actual pulse (A) and a reference pulse (B), the actual pulse (A) is applied to the input terminal (3) of a delay chain (2) having a multiplicity of delay elements (1). The actual pulse (A) enters the delay chain (2) and is held there as determined by a control signal (S) derived from the reference pulse (B). The actual pulse (A) is subsequently shifted out of the delay chain (2), under clock control, the number of delay elements (2) still to be passed determining the phase difference ( phi ). In a circuit arrangement for measuring such small phase differences, the series circuit of a load path of a first transistor (5) of a first inverter (6), a load path of a second transistor (7) and a second inverter (8) are arranged between an input terminal (3) and an output terminal (4) of each delay element (1), the control connections of the first and second transistors (5, 7) being connected to a control device (9).
Inventors:
Ronald Kramer
Peter Plaler
Peter Plaler
Application Number:
JP17884091A
Publication Date:
July 11, 2001
Filing Date:
June 24, 1991
Export Citation:
Assignee:
Siemens Aktiengesellschaft
International Classes:
G01R25/00; G01R25/08; (IPC1-7): G01R25/00
Domestic Patent References:
| JP61227422A | ||||
| JP62140072A | ||||
| JP1267491A |
Attorney, Agent or Firm:
Iwao Yamaguchi