Title:
高速カウントを生成するための方法および回路
Document Type and Number:
Japanese Patent JP3868505
Kind Code:
B2
Abstract:
A counter circuit includes a series of registers driven by two phase shifted clocks. A clock generator in the counter circuit generates four asymmetrical clock signals to drive each of the registers. The registers are formed from input and output stages, each having two sets of switches. The first set of switches in each stage provides a supply voltage to a stage output in response to the asymmetrical clocks. The second set of switches supply ground to the stage output in response to the asymmetrical clocks. To accelerate response of the switching circuits, isolation switches decouple the first set of switches in each pair from the stage output during switching of the second set of switches, thereby removing loading of stage output by the second set of switches.
Inventors:
Manning, Troy A.
Application Number:
JP53878498A
Publication Date:
January 17, 2007
Filing Date:
March 05, 1998
Export Citation:
Assignee:
MICRON TECHNOLOGY,INC.
International Classes:
H03K21/00; H03K23/44; H03K23/00; H03K23/54
Domestic Patent References:
| JP9023153A | ||||
| JP63279616A | ||||
| JP60084015A |
Attorney, Agent or Firm:
Hidesaku Yamamoto
Takaaki Yasumura
Natsuki Morishita
Takaaki Yasumura
Natsuki Morishita