Title:
クロック信号を分周するための方法及び装置
Document Type and Number:
Japanese Patent JP2009502103
Kind Code:
A
Abstract:
There is provided a true single phase logic clock divider that is configured to selectively divide a clock signal by increments of two, three, four, or six. Because the true single phase logic clock divider is based on true single phase logic instead of static logic, the true single phase logic clock divider is able to reliably divide clock signals that could not reliably be divided by clock dividers based on static logic gates. The true single phase logic clock divider is capable of reliably operating at frequencies of greater than or equal to two gigahertz.
Inventors:
Phosphorus, phen
Application Number:
JP2008522928A
Publication Date:
January 22, 2009
Filing Date:
July 17, 2006
Export Citation:
Assignee:
APPLIED MATERIALS,INCORPORATED
International Classes:
H03K23/00; G06F1/08
Attorney, Agent or Firm:
Nomura Yasuhisa
Yoshiyuki Osuga
Yoshiyuki Osuga