Title:
【発明の名称】不揮発性メモリに記憶されたシーケンシャルカウンタのセルの寿命を改良するための方法および装置
Document Type and Number:
Japanese Patent JP2003512695
Kind Code:
A
Abstract:
A method and apparatus for updating and storing a counter value. In response to each of a plurality of N counter update signals, a binary memory cell is selected from a plurality of binary memory cells and the state of the selected binary memory cell is inverted. After the N counter update signals are received, a register that is separate from the plurality of binary memory cells is incremented, and the process is then repeated in response to further counter update signals. Each of the plurality of binary memory cells is inverted on average an equal number of times during each repetition of the process. The states of the plurality of binary memory cells and the value in the register represent the counter value at any given time.
Inventors:
Hutchison, James A. The Force
Spar, Lee Wye
Spar, Lee Wye
Application Number:
JP2001532548A
Publication Date:
April 02, 2003
Filing Date:
October 19, 2000
Export Citation:
Assignee:
QUALCOMM INCORPORATED
International Classes:
G11C16/02; G11C8/04; G11C16/34; H03K21/40; (IPC1-7): G11C16/02
Attorney, Agent or Firm:
Takehiko Suzue (3 outside)