Title:
【発明の名称】高K誘電体キャパシタ及び関連電極のステップカバレッジと境界制御性を高める方法及び装置
Document Type and Number:
Japanese Patent JP2002521846
Kind Code:
A
Abstract:
The present invention provides a multi-layer semiconductor memory device comprising: a bottom electrode having a bottom layer, an upper interface layer and an intermediate tuning layer disposed between the bottom layer and the upper interface layer; a top electrode; and a high dielectric constant dielectric layer disposed between the bottom electrode and the top electrode. The present invention further provides an apparatus and a method for manufacturing high density DRAMs having capacitors having high quality HDC materials and low leakage currents. Another aspect of the present invention provides an electrode-dielectric interface that nucleates high quality HDC films. The present invention further provides an apparatus and a method for manufacturing capacitors within a high aspect ratio aperture.
Inventors:
Dawnfest, Charles
John Egermeyer
Coolana, Nitin
John Egermeyer
Coolana, Nitin
Application Number:
JP2000562958A
Publication Date:
July 16, 2002
Filing Date:
July 27, 1999
Export Citation:
Assignee:
APPLIED MATERIALS,INCORPORATED
International Classes:
H01L27/04; H01L21/02; H01L21/316; H01L21/822; H01L21/8242; H01L27/108; (IPC1-7): H01L21/8242; H01L21/316; H01L21/822; H01L27/04; H01L27/108
Domestic Patent References:
| JPH09191087A | 1997-07-22 | |||
| JPH10173138A | 1998-06-26 | |||
| JPH1050960A | 1998-02-20 | |||
| JPH08330544A | 1996-12-13 | |||
| JPH03257857A | 1991-11-18 | |||
| JPH09102591A | 1997-04-15 |
Foreign References:
| US5555486A | 1996-09-10 |
Attorney, Agent or Firm:
Yoshiki Hasegawa (2 outside)