Title:
【発明の名称】ループの初期化および応答のための方法及び専用のフレームバッファ
Document Type and Number:
Japanese Patent JP2001523862
Kind Code:
A
Abstract:
Cyclic-redundancy-code (“CRC”) information that is received along with a frame from a fiber-channel is stored in an on-chip frame buffer, and later checked to ensure the integrity of the data while in the frame buffer. In various embodiments, data frames, along with their CRC information, are stored into a data-frame buffer, and/or non-data frames along with their CRC information are stored into a receive-non-data-frame buffer. The improved communications channel system includes a channel node having dual ports, each port supporting a fiber-channel arbitrated-loop serial communications channel. The serial communications channels each include CRC on data transmissions on the channel, an on-chip frame memory located on-chip in the channel node that receives a data frame and the frame's associated CRC from the communications channel, and an integrity apparatus that later uses the received associated CRC for data-integrity checking of data in the on-chip frame memory. In addition, a method for using CRC for data integrity in on-chip memory is described.
Inventors:
Westby, Judy, Lynn
Application Number:
JP2000521449A
Publication Date:
November 27, 2001
Filing Date:
November 17, 1998
Export Citation:
Assignee:
Seagate Technology, Incorporated
International Classes:
G06F13/12; G06F3/00; G06F3/06; G06F11/08; G06F11/10; G06F13/00; G06F13/10; G06F13/14; G06F13/368; H03M13/09; H04L1/24; H04L12/42; H04L12/56; G06F11/20; G11B5/012; H04L1/00; (IPC1-7): G06F13/12; G06F13/10
Attorney, Agent or Firm:
Akira Asamura (3 outside)