Title:
Computer-implementable method for simulating the electrical properties of lightning arresters
Document Type and Number:
Japanese Patent JP6356812
Kind Code:
B2
Abstract:
A computer-implementable method for simulating the electrical behavior of a surge arrester comprises providing a model of the surge arrester with a switchable current path between an anode and a cathode of the surge arrester, wherein the current path comprises a controllable voltage source. The current path is switched into the conducting or blocked state depending on a determined value of a voltage rise of an input voltage present between the anode and the cathode and a determined level of a response voltage. A level of the voltage of the controllable voltage source is set depending on a level of a current flowing in the current path.
Inventors:
Hoffman, Robert
Application Number:
JP2016541618A
Publication Date:
July 11, 2018
Filing Date:
November 14, 2014
Export Citation:
Assignee:
EPCOS AG
International Classes:
G06F17/50
Domestic Patent References:
| JP2004266963A | ||||
| JP5333086A |
Foreign References:
| US20050172246 |
Other References:
PSpice Model for Surge Arresters,EPCOS Product Brief 2012 [online],2012年,[検索日 2017.08.29],インターネット,URL,https://en.tdk.eu/download/174062/4a819a8480b723aa0c419d8d163ccde9/pspice-model-surge-arresters-pb.pdf
Attorney, Agent or Firm:
Koji Nagato
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