Title:
The nanowire circuit in the adjusted device
Document Type and Number:
Japanese Patent JP5944377
Kind Code:
B2
Abstract:
A memory device includes a first nanowire connected to a first bit line node and a ground node, a first field effect transistor (FET) having a gate disposed on the first nanowire, a second FET having a gate disposed on the first nanowire, a second nanowire connected to a voltage source node and a first input node, a third FET having a gate disposed on the second nanowire, a third nanowire connected to the voltage source node and a second input node, a fourth FET having a gate disposed on the third nanowire, a fourth nanowire connected to a second bit line node and the ground node, a fifth FET having a gate disposed on the fourth nanowire, and a sixth FET having a gate disposed on the fourth nanowire.
Inventors:
Bangsalun Chip, Sarunya
Cohen, guy
Majmudal, Amrun
Slight, Jeffrey, W
Cohen, guy
Majmudal, Amrun
Slight, Jeffrey, W
Application Number:
JP2013504905A
Publication Date:
July 05, 2016
Filing Date:
March 22, 2011
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION
International Classes:
H01L21/8238; B82Y10/00; B82Y40/00; H01L21/8244; H01L27/092; H01L27/11; H01L29/786
Domestic Patent References:
| JP2007317961A | ||||
| JP2009016418A | ||||
| JP2008172082A | ||||
| JP2008090958A | ||||
| JP2011040524A |
Foreign References:
| WO2005119764A1 |
Attorney, Agent or Firm:
Shinya Mayama
Takeshi Ueno
Tasaichi Tanae
Yoshihiro City
Takeshi Ueno
Tasaichi Tanae
Yoshihiro City
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