Title:
較正のための振動回路と方法
Document Type and Number:
Japanese Patent JP2004516740
Kind Code:
A
Abstract:
An oscillating circuit (10) includes a quartz crystal oscillator (12) for generating a clock signal (20). The clock signal is synchronized to a master signal (19) during the lock-in periods when the oscillating circuit (10) has access to the master signal (19). During the holdover periods when the oscillating circuit (10) loses access to the master signal (19), an oscillation frequency function predicts the crystal oscillation frequency in terms the physical parameters, e.g., time and temperature, that may affect the crystal oscillation frequency. The predicted frequency is compared with a standard frequency to generate an error signal. In response to the error signal, a fraction handler block (28) determines whether adding cycles to or deleting cycles from the clock signal, thereby calibrating the oscillation signal (13) of the oscillating circuit (10).
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Inventors:
Soon, Anthony
Schwartz, blues
Rainson, Kate
Purdy, David
Schwartz, blues
Rainson, Kate
Purdy, David
Application Number:
JP2002552195A
Publication Date:
June 03, 2004
Filing Date:
December 18, 2001
Export Citation:
Assignee:
Telefon Acty Boraget Elm Ericsson
International Classes:
G04G7/00; H03B5/32; H03L1/00; G06F1/12; H03L1/02; H03L7/00; (IPC1-7): H03L1/00; G06F1/12; H03B5/32
Attorney, Agent or Firm:
Hideto Asamura
Hajime Asamura
Hayashi Zouzo
Eiichi Sobue
Hajime Asamura
Hayashi Zouzo
Eiichi Sobue