Title:
較正のための振動回路と方法
Document Type and Number:
Japanese Patent JP4050618
Kind Code:
B2
Abstract:
An oscillating circuit (10) includes a quartz crystal oscillator (12) for generating a clock signal (20). The clock signal is synchronized to a master signal (19) during the lock-in periods when the oscillating circuit (10) has access to the master signal (19). During the holdover periods when the oscillating circuit (10) loses access to the master signal (19), an oscillation frequency function predicts the crystal oscillation frequency in terms the physical parameters, e.g., time and temperature, that may affect the crystal oscillation frequency. The predicted frequency is compared with a standard frequency to generate an error signal. In response to the error signal, a fraction handler block (28) determines whether adding cycles to or deleting cycles from the clock signal, thereby calibrating the oscillation signal (13) of the oscillating circuit (10).
Inventors:
Soon, Anthony
Schwartz, blues
Rainson, Kate
Purdy, David
Schwartz, blues
Rainson, Kate
Purdy, David
Application Number:
JP2002552195A
Publication Date:
February 20, 2008
Filing Date:
December 18, 2001
Export Citation:
Assignee:
Telefon Akti Bora Get Elm Ericson (Pubble)
International Classes:
G06F1/12; G04G7/00; H03L1/00; H03B5/32; H03L1/02; H03L7/00
Domestic Patent References:
| JP2000036739A | ||||
| JP2000196444A | ||||
| JP54163660A | ||||
| JP7321644A | ||||
| JP7181273A |
Attorney, Agent or Firm:
Yasunori Otsuka
Shiro Takayanagi
Yasuhiro Otsuka
Shuji Kimura
Osamu Shimoyama
Hayashi Zouzo
Eiichi Sobue
Shiro Takayanagi
Yasuhiro Otsuka
Shuji Kimura
Osamu Shimoyama
Hayashi Zouzo
Eiichi Sobue