PURPOSE: To form an element isolation area, base lead-out region, base and emitter regions in a self alignment manner, and reducing the area of the element, and integrating this device, and reduce base-emitter junction capacity, and increase the operation speed of a transistor.

CONSTITUTION: An n-type buried layer 2 is formed on a p-type semiconductor substrate 1, and an n-type epitaxial layer 3 is grown all over the surface, and leaving an oxide film 5 only on the emitter formation part, a nitride film 6 is formed on the sidewall of the oxide film 5, and an oxide film 7 for element isolation is formed, and the nitride film 6 is removed. Next, a polycrystalline silicon 8 for base leadout is formed, and an insulating film is formed, and the insulating film on the oxide film 5 is removed, and an exposed oxide film 5 is removed, and the polycrystalline silicon on the sidewall is oxidized, and a base region 15 is formed by ion implantation, and a nitride film 19 is formed on the sidewall, and after removal of the oxide film on the base region 15, a polycrystalline silicon 16 is grown selectively, ions of arsenic are implanted and by the diffusion from the polycrystalline silicon 16, an emitter region 17 is formed.