Title:
AUTOMATIC TERMINAL LOAD SETTING DEVICE
Document Type and Number:
Japanese Patent JP3070570
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To classify many circuits that supply a high frequency signal with identical characteristic impedance, to automatically set the same Tevenins terminal load to the respective groups and to make the setting work easy and sure.
SOLUTION: A clock signal from a clock generator 2a of an individual circuit board 2 is supplied to terminal load setting parts 3a and 4a through circuit patterns 21a and 23a. Arrangement position identifying parts 3b and 4b send an on-signal or an off-signal which identifies the arrangement positions (corresponding to the lengths (characteristic impedance of termination) of circuit patterns 21a and 23b from the generator 2a to an input terminal of a clock signal of an extended buffer) of the parts 3a and 4a on an arrangement substrate 1. Resistance value, that forms Tevenins terminal load corresponding to characteristic impedance in an input terminal of a buffer to which clock signals of the parts 3a and 4a are supplied, is selected by the on and off signals and is automatically set.
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Inventors:
Yoshinobu Ueki
Application Number:
JP4308998A
Publication Date:
July 31, 2000
Filing Date:
February 25, 1998
Export Citation:
Assignee:
NEC
International Classes:
H03K19/0175; H04L25/02; (IPC1-7): H03K19/0175
Attorney, Agent or Firm:
Kihei Watanabe
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