Title:
分周回路およびPLL回路
Document Type and Number:
Japanese Patent JP5372114
Kind Code:
B2
Abstract:
A frequency divider of an injection locked type capable of division by 2, division by 4, and further division by 8 with a simpler configuration is disclosed and the frequency divider includes a ring oscillator including M (M is an even number) delay elements, the tails of two delay elements M/2 delay elements apart from each other are connected to a differential pair and transistors, to the gates of which the input oscillation signal is applied, are connected to the differential pair, and the differential pair is caused to generate a differential signal of the input oscillation signal, which is a divide-by-2 signal of the input oscillation signal, and when dividing the frequency of the input oscillation signal by 8, the portion of the differential pair to be connected to the tail of the delay element is caused to have a two-stage configuration, which is a vertically stacked configuration.
More Like This:
| JPS5651109 | FREQUENCY DIVIDER |
| WO/2002/086838 | SAFETY DEVICE |
Inventors:
Kenichi Okada
Ahmed Magdi Hassan Musa
Ahmed Magdi Hassan Musa
Application Number:
JP2011246362A
Publication Date:
December 18, 2013
Filing Date:
November 10, 2011
Export Citation:
Assignee:
Semiconductor Science and Engineering Research Center Co., Ltd.
International Classes:
H03K27/00; H03K5/00; H03K23/52; H03K23/54; H03L7/08
Domestic Patent References:
| JP201161325A |
Foreign References:
| WO2007072549A1 |
Attorney, Agent or Firm:
Atsushi Aoki
Jun Tsuruta
Koichi Itsubo
Tomohiro Minamiyama
Jun Tsuruta
Koichi Itsubo
Tomohiro Minamiyama