Title:
【発明の名称】半導体装置
Document Type and Number:
Japanese Patent JP3130809
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor device of a PKG (3-pin, small minimold package) structure which can be manufactured inexpensively and easily with low costs and with a sufficient inductance and excellent low noise characteristics. SOLUTION: A GaAs FET 104 is mounted on a chip mount area 105 of a lead frame having a lead terminal 101 with an end 101a of a spiral coil shape. The lead terminals 101, 102 and 103 are connected to gate, drain and source electrodes 107, 108 and 109 respectively, and the sealed with epoxy resin 110.
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Inventors:
Suguru Satoh
Application Number:
JP30848696A
Publication Date:
January 31, 2001
Filing Date:
November 19, 1996
Export Citation:
Assignee:
NEC
International Classes:
H01F17/00; H01L21/60; H01L23/31; H01L25/00; H01L23/29; (IPC1-7): H01L21/60; H01F17/00; H01L21/60; H01L23/29; H01L23/31; H01L25/00
Domestic Patent References:
| JP697315A | ||||
| JP4165655A | ||||
| JP7202056A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)