Title:
A pin arrangement design of a laminated type memory package, its manufacturing method, and an IC package board
Document Type and Number:
Japanese Patent JP6081655
Kind Code:
B2
Abstract:
Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides.
Inventors:
Phi Anthony
Boyle Evan Earl
Yangji Pin
Wu Junghwa
Boyle Evan Earl
Yangji Pin
Wu Junghwa
Application Number:
JP2016500129A
Publication Date:
February 15, 2017
Filing Date:
December 19, 2013
Export Citation:
Assignee:
Apple Inc.
International Classes:
H01L25/065; H01L25/07; H01L25/18
Foreign References:
| US20110037158 | ||||
| US20130049228 | ||||
| WO2005053025A1 |
Attorney, Agent or Firm:
Takaki Nishijima
Disciple Maru Ken
Shinichiro Tanaka
Fumiaki Otsuka
Disciple Maru Ken
Shinichiro Tanaka
Fumiaki Otsuka