ABNORMALITY DETECTOR OF CPU

Japanese Patent JP3214079

B2

PURPOSE: To provide the abnormality detector of a CPU suitable for applying to the servo system of a VTR.
CONSTITUTION: The output signal level 13 of an O port 2 is turned to an H level while the CPU 1 executes a prescribed processing program stored in a ROM 4 and is turned to an L level after completion based on the interruption signals 11 of an interruption signal generator 5. At the time of the L level before the next interruption signal arrives, the abnormality detector 3 latches the L level and detects that the CPU 1 is not abnormal. When the CPU 1 becomes abnormal while executing the program and an abnormal state continues even when the interruption signal 11 arrives, the output level of the O port 2 is the H level and the abnormality detector 3 latches the H level, detects that the CPU is abnormal, and turns off the power source of the motor of the servo system of the VTR. The abnormality detection of nonregular processing impossible by a watchdog timer is enabled.

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Yasuo Nagai

JP21340692A

October 02, 2001

July 17, 1992

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ソニー株式会社

G06F11/30; (IPC1-7): G06F11/30

JP4111138A
JP614232A
JP6252645A
JP1204159A
JP2259935A
JP3152637A

Takashi Shibuya

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