昇圧電位発生回路及び制御方法 - エルピーダメモリ株式会社

Title:

昇圧電位発生回路及び制御方法

Document Type and Number:

Japanese Patent JP4257064

Kind Code:

B2

Abstract:

A boosted potential generation circuit enables a high-speed operation and even miniaturization in a semiconductor memory even if external power supply voltage is reduced in the semiconductor memory. In the boosted potential generation circuit provided with a capacitor MOS transistor and a transfer MOS transistor and used for a DRAM including memory cells, a gate insulating film of the capacitor MOS transistor is thinner than that of the MOS transistor constituting the memory cell to realize a boosted potential generation circuit which has a small area and a large capacity. In this case, preferably, the gate insulating film of the transfer MOS transistor has a thickness which is not greater than that of the gate insulating film of the capacitor MOS transistor.

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Inventors:

久保内修一
前健治
成井誠司
森野誠

Application Number:

JP2002044533A

Publication Date:

April 22, 2009

Filing Date:

February 21, 2002

Export Citation:

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Assignee:

エルピーダメモリ株式会社

International Classes:

G11C11/407; G11C11/4074; G11C5/14; H01L21/822; H01L21/8242; H01L27/04; H01L27/10; H01L27/108; H02M3/07

Attorney, Agent or Firm:

佐々木敬
池田憲保
福田修一

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