Title:
POWER AMPLIFICATION CIRCUIT
Document Type and Number:
Japanese Patent JP2023073644
Kind Code:
A
Abstract:
To suppress a change in gain.SOLUTION: A power amplification circuit includes: a plurality of amplification transistors connected in cascade, each amplification transistor amplifying a signal supplied to a base and outputting the amplified signal; a first resistor element having a first end and a second end connected to a base of a first amplification transistor; a second resistor element having a first end and a second end connected to a base of a second amplification transistor corresponding to the amplification transistor on the input side relative to the first amplification transistor; a first bias supply transistor including an emitter connected to the first end of the first resistor element; a second bias supply transistor including an emitter connected to the first end of the second resistor element; and a bias current compensation transistor including a base connected to the first end of the first resistor element, a collector connected to the first end of the second resistor element, and an emitter connected to the ground.SELECTED DRAWING: Figure 1
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Inventors:
HASE MASATOSHI
Application Number:
JP2021186221A
Publication Date:
May 26, 2023
Filing Date:
November 16, 2021
Export Citation:
Assignee:
MURATA MANUFACTURING CO
International Classes:
H03F1/32; H03F3/21; H03F3/68
Attorney, Agent or Firm:
Yoshiyuki Inaba
Toshifumi Onuki
Akihiko Eguchi
Kazuhiko Naito
Mutsumi Sato
Toshifumi Onuki
Akihiko Eguchi
Kazuhiko Naito
Mutsumi Sato