Title:
【発明の名称】半導体パッケージ用回路基板の製造方法
Document Type and Number:
Japanese Patent JP3382482
Kind Code:
B2
Abstract:
In a method for producing a circuit board for a semiconductor package, portions of the resist film formed on the respective surface of the core substrate are removed during the exposure/development process, which portions correspond to the circuit pattern and to the cavity opening but having a diameter smaller than that of the cavity opening, whereby the photosensitive portion of the resist film is hardened while extending inward from the upper edge of the cavity opening to a predetermined distance. The resist film operates as a resist for the conductor layer to be formed on the inner wall of the cavity opening and connected to the circuit pattern on one surface of the core substrate. Thereby, since the finally formed conductor layer does not reach the upper edge of the cavity opening at a predetermined vacant space therefrom, short-circuiting of the signal line is prevented from occurring even if the bonding wire is brought into contact with the upper edge of the cavity opening. Thus, it is possible to improve the yield in the production of plastic packages as well as the quality of the resultant packages.
Inventors:
Hiroharu Sato
Masayoshi Ebe
Masayoshi Ebe
Application Number:
JP33704596A
Publication Date:
March 04, 2003
Filing Date:
December 17, 1996
Export Citation:
Assignee:
Shinko Electric Industry Co., Ltd.
International Classes:
H01L21/60; H01L21/48; H01L23/12; H01L23/498; H05K3/00; H05K3/18; H05K3/42; H05K3/46; H05K3/10; (IPC1-7): H01L23/12; H01L21/60
Domestic Patent References:
| JP457385A | ||||
| JP6152143A |
Attorney, Agent or Firm:
Takao Watanuki (1 outside)