Title:
薄膜積層デバイス、回路および薄膜積層デバイスの製造方法
Document Type and Number:
Japanese Patent JP4191959
Kind Code:
B2
Abstract:
The present invention provides a novel capacitor element, laminated thin-film device, and circuit wherein the capacitance dependency on voltage can be appropriately adjusted, and a technology for manufacturing such a capacitor element and laminated thin-film device. In the capacitor element that comprises a pair of electrode layers and a dielectric layer disposed between the electrode layers, a well region where an ion is implanted is disposed in the dielectric layer, and the C-V curve between the electrode layers is shifted or shifted and expanded in at least one direction of the plus direction and minus direction with respect to the voltage axis.
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Inventors:
John David Vannick
Kenji Shioga
Kurihara Kazuaki
Kenji Shioga
Kurihara Kazuaki
Application Number:
JP2002181463A
Publication Date:
December 03, 2008
Filing Date:
June 21, 2002
Export Citation:
Assignee:
富士通株式会社
International Classes:
H01G7/06; H01L21/822; H01L21/02; H01L27/04
Domestic Patent References:
| JP10178153A | ||||
| JP6013572A | ||||
| JP5343641A | ||||
| JP2106068A |
Attorney, Agent or Firm:
Kenji Doi
Hayashi Tsunetoku
Hayashi Tsunetoku