PULSE WIDTH MODULATOR AND PROGRAM THEREFOR

Japanese Patent JP2017098671

A

PROBLEM TO BE SOLVED: To provide a pulse width modulator including a ΔΣ modulator capable of obtaining an excellent pulse width modulated signal by stabilizing operation of signal processing without increasing the number of times of arithmetic operation even when providing a limiter, and a program therefor.SOLUTION: The pulse width modulator comprises: a subtraction part for subtracting an m-value digital signal and a pulse width modulation signal; a feedforward filter part to which an output signal of the subtraction part is inputted and a ΔΣ modulator including second-order or higher-order integrators is cascaded and which is operated in a sampling frequency FS; a sum-of-product calculation part which is operated in a sampling frequency (FS/n)((n) is an integer equal to or greater than 2) for calculating a sum of products regarding output signals from the integrators; an integrator control part which resets values held by delay devices of the integrators in the feedforward filter part to zero in the case where an absolute value of an output signal of the sum-of-product calculation part exceeds a predetermined threshold value; and a pulse width modulation part which performs pulse width modulation on the output signal of the sum-of-product calculation part and outputs a pulse width modulated signal.SELECTED DRAWING: Figure 1

TACHIMORI SHINYA

JP2015226873A

June 01, 2017

November 19, 2015

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ONKYO KK

H03M3/02; H03K7/08

JP4116005B2	2008-07-09
JP2007208376A	2007-08-16
JP2010109436A	2010-05-13

US20070194827A1	2007-08-23
US20050093727A1	2005-05-05
US5012244A	1991-04-30
US6362763B1	2002-03-26

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