PURPOSE: To make it possible to execute optional frequency division only by the use of one oscillation circuit by changing a frequency dividing ratio in each cycle.

CONSTITUTION: This clock frequency dividing circuit is provided with a down counter C, a selection circuit S and a control circuit CRT. The down counter C counts up a set value and outputs two output signals when the counted value is the set value and a value next to the set value. Namely a clock inputted to an input terminal 1 is inputted to a down counter and counted. When the count value becomes '1' and an output (b) is turned to '0', an output (a) is turned to a high level. Two outputs of the down counter C are selected at a fixed rate by a selection circuit S and a control circuit CTR and the selected output is outputted from an output terminal O to obtain frequency division other than 1/n (n: natural number). In the case of attaining 2/9 frequency division e.g. 2 pulses are allowed to be outputted in each input of 9 clocks. Thereby frequency division can be attained by alternately executing 4 and 5 frequency division.