Title:
【発明の名称】導通試験システム及びATM試験装置
Document Type and Number:
Japanese Patent JP3042518
Kind Code:
B1
Abstract:
PROBLEM TO BE SOLVED: To obtain a continuity test system which can conduct a continuity test while minimizing hit of user data even in service wherein the user data flow on a transmission line including an ATM section and an STM section. SOLUTION: When a loop-back test is conducted by regarding the loop-back point of a loop-back test cell outputted by the ATM testing device 4 as the decelling part 34 of cell assembly and disassembly(CLAD) 3, the CLAD 3 includes the received loop-back test cell as STM data in the same frame with loop-back control information and sends them to DSU 2, but the frame of the loop-back control information is sent preferentially by discarding user data transmitted from the CLAD 3 to the DSU 2 or the like. When the received STM data including loop-back information, the data which are sent at the same time are sent back to the CLAD 3 as they are, but overwritten to the frame of the user data so as to given priority to the frame of loop-back control information.
Inventors:
Jun Aizawa
Application Number:
JP35369898A
Publication Date:
May 15, 2000
Filing Date:
December 14, 1998
Export Citation:
Assignee:
NEC
International Classes:
H04J3/00; H04J3/14; H04L12/28; H04L69/40; H04Q3/00; (IPC1-7): H04L12/28; H04J3/00; H04L12/26; H04L29/14
Domestic Patent References:
| JP746253A |
Attorney, Agent or Firm:
Akihiko Nakazawa