Title:
MULTILAYER WIRING BOARD
Document Type and Number:
Japanese Patent JP3206561
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a multilayer wiring board which can eliminate noise which disturbs the waveform of a signal transmitted through a through-hole.
SOLUTION: A multilayer wiring board 100 comprises ground patterns 1210 and 1220, power supply patterns 1310 and 1320, a wiring pattern 1432 formed on a signal wiring layer 143 provided between the ground pattern 1220 and the power supply pattern 1320, and a through-hole 112 which is connected to the wiring pattern 1432 and pierces through the ground patterns 1210 and 1220 and the power supply patterns 1310 and 1320. A clearance 173 is formed between the ground pattern 1220 and the through-hole 112. A clearance 171 larger than the clearance 173 is formed between the ground pattern 1210 and the through- hole 112.
Inventors:
Naoki Kobayashi
Application Number:
JP28008898A
Publication Date:
September 10, 2001
Filing Date:
October 01, 1998
Export Citation:
Assignee:
NEC
International Classes:
H05K3/46; H05K1/02; H05K1/11; H05K3/42; (IPC1-7): H05K3/46
Domestic Patent References:
| JP9321433A | ||||
| JP3257991A | ||||
| JP53101263U |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)