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Title:
SEMICONDUCTOR CHIP TESTING DEVICE AND SEMICONDUCTOR CHIP TESTING METHOD
Document Type and Number:
Japanese Patent JP2017040561
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a technique capable of preventing generation of electrical discharge at a time of measuring electrical characteristics of a test object.SOLUTION: The semiconductor chip testing device is provided with: a lower fixture 8; a contact pin 1; an upper fixture 7 which is disposed above a semiconductor chip 6, which is the test object, and to which the contact pin 1 is secured; an insulation wall 3 that is disposed at a position surrounding side surfaces of the semiconductor chip 6 and is capable of sealing the semiconductor chip 6 cooperatively with the upper fixture 7 and the lower fixture 8; gas injection ports 2 disposed in the upper fixture 7 so as to be capable of injecting an insulation gas toward the surfaces of the semiconductor chip 6; and a gas supply part 12 that supplies the insulation gas to the gas injection ports 2. The gas supply part 12 is configured to supply the insulation gas to the gas injection ports 2 at a preset cycle when the semiconductor chip 6 is placed on the lower fixture 8 without being sealed.SELECTED DRAWING: Figure 1

Inventors:
TAKAGI YASUSHI
Application Number:
JP2015162476A
Publication Date:
February 23, 2017
Filing Date:
August 20, 2015
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G01R31/26; G01R31/28; H01L21/66
Domestic Patent References:
JP2015035577A2015-02-19
JP2013030647A2013-02-07
JP2012189674A2012-10-04
JP2015053416A2015-03-19
JP2007050352A2007-03-01
JPH11238770A1999-08-31
JP2000164648A2000-06-16
JP2013258386A2013-12-26
JPH02106050A1990-04-18
JPH0637121A1994-02-10
JP2014145615A2014-08-14
Foreign References:
US20130043875A12013-02-21
WO2012026036A12012-03-01
Attorney, Agent or Firm:
Yoshitake Hidetoshi
Takahiro Arita