Title:
自己整合型の半導体メサおよびコンタクト層を有する半導体デバイス、および、該デバイスに関連する構造の形成方法
Document Type and Number:
Japanese Patent JP4866550
Kind Code:
B2
Abstract:
A method of forming a semiconductor device may include forming a semiconductor structure (14) on a substrate (12) wherein the semiconductor structure (14) defines a mesa (20) having a mesa surface (20A) opposite the substrate (12) and mesa sidewalls between the mesa surface and the substrate. A first passivation layer (30) can be formed on at least portions of the mesa sidewalls and on the substrate (12) adjacent the mesa sidewalls wherein at least a portion of the mesa surface (20A) is free of the first passivation layer (30) and wherein the first passivation layer (30) comprises a first material. A second passivation layer (40) can be formed on the first passivation layer (30) wherein at least a portion of the mesa surface (20A) is free of the second passivation layer (40), and wherein the second passivation layer (40) comprises a second material different than the first material. Related devices are also discussed.
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Inventors:
Kevin W. Harberan
Michael Jay Bergman
Raymond Rosad
David T. Emerson
Michael Jay Bergman
Raymond Rosad
David T. Emerson
Application Number:
JP2004563767A
Publication Date:
February 01, 2012
Filing Date:
December 18, 2003
Export Citation:
Assignee:
CREE INC.
International Classes:
H01S5/227; C30B1/00; H01L21/00; H01L33/14; H01S5/042; H01S5/22; H01S5/223; H01S5/323; H01S5/343
Domestic Patent References:
| JPH07221081A | 1995-08-18 | |||
| JPH04276682A | 1992-10-01 | |||
| JPH05190968A | 1993-07-30 | |||
| JP2000299528A | 2000-10-24 | |||
| JP2000058965A | 2000-02-25 |
Attorney, Agent or Firm:
Asamura patent office
Hideto Asamura
Hajime Asamura
Kazuyuki Ohinata
Hayashi Zouzo
Kuniaki Shimizu
Takayuki Hatanaka
Akira Iwami
Hideto Asamura
Hajime Asamura
Kazuyuki Ohinata
Hayashi Zouzo
Kuniaki Shimizu
Takayuki Hatanaka
Akira Iwami