Title:
半導体装置
Document Type and Number:
Japanese Patent JP7116214
Kind Code:
B2
Abstract:
An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.
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Inventors:
Sanpei Yamazaki
Hiroki Ohara
Toshinari Sasaki
Kosei Noda
Hideaki Kuwahara
Hiroki Ohara
Toshinari Sasaki
Kosei Noda
Hideaki Kuwahara
Application Number:
JP2021064402A
Publication Date:
August 09, 2022
Filing Date:
April 05, 2021
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H01L29/786; H01L21/336
Domestic Patent References:
| JP2009135188A | ||||
| JP2009075385A | ||||
| JP2009099887A | ||||
| JP2009141002A | ||||
| JP2007123861A |
Foreign References:
| WO2007063966A1 |
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