Title:
半導体装置
Document Type and Number:
Japanese Patent JP7118785
Kind Code:
B2
Abstract:
A semiconductor device includes first and second chips that are stacked such that first surfaces of their element layers face each other. Each chip has a substrate, an element layer on a first surface of the substrate, pads on the element layer, and vias that penetrate through the substrate and the element layer. Each via is exposed from a second surface of the substrate and directly connected to one of the pads. The vias include a first via of the first chip directly connected to a first pad of the first chip and a second via of the second chip directly connected to a second pad of the second chip. The pads further include a third pad of the second chip which is electrically connected to the second pad by a wiring in the element layer of the second chip and to the first pad through a micro-bump.
Inventors:
Koyanagi Masaru
Application Number:
JP2018132427A
Publication Date:
August 16, 2022
Filing Date:
July 12, 2018
Export Citation:
Assignee:
Kioxia Co., Ltd.
International Classes:
H01L25/065; G11C5/04; H01L21/3205; H01L21/768; H01L21/822; H01L23/522; H01L25/07; H01L25/18; H01L27/04
Domestic Patent References:
| JP2003021666A |
Foreign References:
| US20110248396 | ||||
| WO2016042603A1 | ||||
| WO2013021847A1 | ||||
| KR1020130018812A |
Attorney, Agent or Firm:
Masatoshi Kurata
Nobuhisa Nogawa
Ryuji Mine
Naoki Kono
Ken Ukai
Nobuhisa Nogawa
Ryuji Mine
Naoki Kono
Ken Ukai
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