Title:
半導体装置
Document Type and Number:
Japanese Patent JP7334638
Kind Code:
B2
Abstract:
To suppress the deterioration of an interlayer insulating film below a gate wire.SOLUTION: A semiconductor device includes a semiconductor substrate including a transistor, a source electrode disposed on the semiconductor substrate and connected to a source of the transistor, an interlayer insulating film disposed on the semiconductor substrate, and a gate wire disposed on the interlayer insulating film and connected to a gate of the transistor. The semiconductor substrate includes a first p-type region, an n-type region, and a second p-type region. The first p-type region is in contact with the interlayer insulating film below the gate wire. The n-type region is in contact with the first p-type region. The second p-type region is in contact with the n-type region, separated from the first p-type region by the n-type region, and is in contact with the source electrode.SELECTED DRAWING: Figure 1
Inventors:
Ryuta Suzuki
Katsuhiro Kuchiki
Katsuhiro Kuchiki
Application Number:
JP2020019761A
Publication Date:
August 29, 2023
Filing Date:
February 07, 2020
Export Citation:
Assignee:
株式会社デンソー
International Classes:
H01L29/78; H01L29/06; H01L29/12
Domestic Patent References:
| JP2015211159A |
Foreign References:
| WO2018155566A1 | ||||
| WO2018155553A1 | ||||
| WO2019123717A1 | ||||
| WO2011007387A1 | ||||
| WO2019124378A1 | ||||
| WO2015178024A1 |
Attorney, Agent or Firm:
Patent Attorney Corporation Kaiyu International Patent Office
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