Title:
半導体装置
Document Type and Number:
Japanese Patent JP7411531
Kind Code:
B2
Abstract:
A semiconductor device includes a memory mat having: a plurality of memory cells; a sense amplifier connected to a memory cell selected from the plurality of memory cells; a first power supply wiring; a first switch connected between the sense amplifier and the first power supply wiring and made an ON state in operating the sense amplifier; and a second switch connected to the sense amplifier and made an ON state in operating the sense amplifier, a second power supply wiring arranged outside the memory mat and connected to the first power supply wiring, a third power supply wiring arranged outside the memory mat and connected to the sense amplifier via the second switch, and a short switch arranged outside the memory mat and connected between the second and third power supply wirings. Here, in operating the sense amplifier, the short switch is made an ON state.
Inventors:
Fukushi Tetsuo
Hiroyuki Takahashi
Muneaki Matsushige
Hiroyuki Takahashi
Muneaki Matsushige
Application Number:
JP2020177830A
Publication Date:
January 11, 2024
Filing Date:
October 23, 2020
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
G11C11/4091; G11C11/4074
Domestic Patent References:
| JP201181855A | ||||
| JP2007149312A | ||||
| JP11121717A |
Attorney, Agent or Firm:
Patent Attorney Tsutsui International Patent Office