Title:
半導体装置
Document Type and Number:
Japanese Patent JP7413329
Kind Code:
B2
Abstract:
A semiconductor device (1) is manufactured which includes a SiC epitaxial layer (28), a plurality of transistor cells (18) that are formed in the SiC epitaxial layer (28) and that are subjected to ON/OFF control by a predetermined control voltage, a gate electrode (19) that faces a channel region (32) of the transistor cells (18) in which a channel is formed when the semiconductor device (1) is in an ON state, a gate metal (44) that is exposed at the topmost surface for electrical connection with the outside and that is electrically connected to the gate electrode (19) while being physically separated from the gate electrode (19), and a built-in resistor (21) that is made of polysilicon and that is disposed below the gate metal (44) so as to electrically connect the gate metal (44) and the gate electrode (19) together.
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Inventors:
Katsuhisa Nagao
Noriaki Kawamoto
Noriaki Kawamoto
Application Number:
JP2021152878A
Publication Date:
January 15, 2024
Filing Date:
September 21, 2021
Export Citation:
Assignee:
ROHM Co., Ltd.
International Classes:
H01L29/78; H01L21/822; H01L21/8234; H01L27/04; H01L27/06; H01L27/088; H01L29/12; H01L29/739
Domestic Patent References:
| JP2003197914A | ||||
| JP2007042817A | ||||
| JP2002368218A | ||||
| JP2004172448A | ||||
| JP2002083964A | ||||
| JP2001250948A | ||||
| JP1305576A | ||||
| JP2013045996A | ||||
| JP2010087124A | ||||
| JP2008277365A |
Attorney, Agent or Firm:
Patent Attorney Corporation Ai Patent Office