Title:
半導体装置
Document Type and Number:
Japanese Patent JP7434497
Kind Code:
B2
Abstract:
In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock signal is not supplied. A channel formation region of the transistor is formed using an oxide semiconductor in which the hydrogen concentration is reduced. Specifically, the hydrogen concentration of the oxide semiconductor is 5×1019 (atoms/cm3) or lower. Thus, leakage current of the transistor can be reduced. As a result, in the logic circuit, reduction in standby power and suppression of malfunction can be achieved.
Inventors:
Yutaka Shionoiri
Hidetomo Kobayashi
Hidetomo Kobayashi
Application Number:
JP2022177118A
Publication Date:
February 20, 2024
Filing Date:
November 04, 2022
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H01L21/336; H01L21/822; H01L21/8234; H01L21/8238; H01L27/04; H01L27/088; H01L27/092; H01L29/786; H03K19/00; H03K19/096
Domestic Patent References:
| JP2009135350A | ||||
| JP2006165532A | ||||
| JP2009535819A | ||||
| JP8274195A | ||||
| JP200938368A |
Foreign References:
| US20090114918 |