Title:
A semiconductor memory device and a method for controlling the same
Document Type and Number:
Japanese Patent JP6221806
Kind Code:
B2
Abstract:
A semiconductor memory device includes: a memory cell array including a memory cell, which includes a ferroelectric capacitor and an access transistor which is a first conductive type transistor formed in a second conductive type well and includes a source or a drain connected to one electrode of the ferroelectric capacitor; and a control circuit which controls a potential applied to the second conductive type well. The control circuit applies a fixed potential to another electrode of the ferroelectric capacitor and applies a second potential being a forward voltage with respect to a junction between the first conductive type source and drain and the second conductive type well when erasing data in the memory cell, and applies a third potential not being the forward voltage with respect to the junction between the first conductive type source and drain and the second conductive type well in a normal operation.
Inventors:
Shoichiro Kawashima
Application Number:
JP2014026608A
Publication Date:
November 01, 2017
Filing Date:
February 14, 2014
Export Citation:
Assignee:
Fujitsu Semiconductor Limited
International Classes:
G11C11/22
Domestic Patent References:
| JP2000048577A | ||||
| JP2004153239A | ||||
| JP2010251491A | ||||
| JP2007150198A |
Attorney, Agent or Firm:
Takayoshi Kokubun
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