SEMICONDUCTOR MEMORY DEVICE

Japanese Patent JP2023140604

A

To provide a suitably operating semiconductor memory device.SOLUTION: A semiconductor memory device includes a memory cell array and a peripheral circuit. The memory cell array includes a plurality of first semiconductor layers and a plurality of first via electrodes. The peripheral circuit includes: a plurality of first nodes provided corresponding to a plurality of first via electrodes; a charging circuit for charging the plurality of first nodes; a discharging circuit for discharging the plurality of first nodes; an address selection circuit for conducting one of the plurality of first nodes with a charging circuit or a discharging circuit in response to an input address signal; a plurality of first transistors provided respectively in a current path between two of the plurality of first nodes; and a plurality of amplification circuits provided corresponding to the plurality of first via electrodes and provided with an input terminal connected to one of the plurality of first nodes and an output terminal connected to one of the plurality of first via electrodes.SELECTED DRAWING: Figure 17

JPH0632227	INDUSTRIAL APPLICABILITY: An electrically erasable and programmable semiconductor memory device having a NAND cell, and an erasing method and programming method in the device.
JP3970299	SEMICONDUCTOR MEMORY DEVICE
JP5285064	Multi-level cell access buffer with dual function

HOSOYA KEIJI
ARAI FUMITAKA
KOSAKO HIROAKI
KAKEGAWA TAKAYUKI
NAITO SHINYA
FUKUOKA RYO
MATSUO KOJI

JP2022046520A

October 05, 2023

March 23, 2022

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KIOXIA CORP

G11C16/04; G11C16/08; H01L21/336; H10B41/27; H10B41/40; H10B41/50

Kisaragi International Patent Office

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