Title:
【発明の名称】半導体装置
Document Type and Number:
Japanese Patent JP3092133
Kind Code:
B2
Abstract:
PURPOSE:To complete a wiring layout of cross connection between adjacent gates by using only a first layer wiring of short distance, by a method wherein the gate terminal leading-out part of a first insulated gate type field effect transistor is constituted in such a shape and area as provided with a first wiring contact region and a second wiring contact region. CONSTITUTION:Each of the polysilicon gates 14P, 15P are constituted of the following; a narrow width type gate electrode part (g) having effectively a 4-grids length, and gate terminal leading-out parts T1, T2 having about 1-grid areas of approximate square connected with both ends of said part (g). These gate terminal leading-out parts T1, T2 have areas capable of wire coating via a single contact hole for single wiring connection position, i.e., ohmic contact. By using only a first layer Al wiring without using a second layer A (wiring, mutual connection is enabled, in a space of 3 grids in the X-direction and 2 grids in the Y-direction formed by a first wiring connection position t1, and a first wiring connection position t1 of the terminal leading-out part T1' of a gate 14N.
Inventors:
Kazuhiko Ohkawa
Takashi Sakuta
Yasuhiro Oguchi
Yasuhisa Hirabayashi
Takashi Sakuta
Yasuhiro Oguchi
Yasuhisa Hirabayashi
Application Number:
JP2778590A
Publication Date:
September 25, 2000
Filing Date:
February 07, 1990
Export Citation:
Assignee:
Seiko Epson Corporation
International Classes:
H01L27/118; H01L21/82; H01L27/088; (IPC1-7): H01L27/118
Domestic Patent References:
| JP6135535A | ||||
| JP63306639A |
Attorney, Agent or Firm:
Kisaburo Suzuki (1 outside)