Title:
半導体メモリ素子の信号伝達制御装置
Document Type and Number:
Japanese Patent JP4999584
Kind Code:
B2
Abstract:
A signal delay control circuit for use in a semiconductor memory device is disclosed. The circuit includes a first reference voltage generating unit for generating a first reference voltage; a second reference voltage generating unit for generating a second reference voltage that is lower than the first reference voltage; a control signal generating unit for generating a clock signal to drive input and output operations of internal circuits; and an impedance circuit in circuit with the first and second reference voltage generating units for generating a plurality of reference voltages to be applied to the internal circuits wherein the reference voltages are set in accordance with a distance between the control signal generating unit and the respective one of the internal circuits.
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Inventors:
Lee
Application Number:
JP2007187446A
Publication Date:
August 15, 2012
Filing Date:
July 18, 2007
Export Citation:
Assignee:
SK hynix Inc.
International Classes:
G11C11/407; G11C11/4091; G11C5/14; G11C7/00; G11C7/06; G11C7/10; G11C7/22; G11C11/401; G11C11/408; G11C11/409
Domestic Patent References:
| JP2183493A | ||||
| JP785670A |
Attorney, Agent or Firm:
Eiji Saegusa
Shinichi Mashita
Kimio Matsumoto
Shinichi Mashita
Kimio Matsumoto