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Patent Searching and Data


Title:
FRAME TRANSMISSION SYSTEM
Document Type and Number:
Japanese Patent JPH0723013
Kind Code:
A
Abstract:

PURPOSE: To contain a specific signal in a frame of a parity frame system by using a bit allocated to a specific line of a multi-frame as a control bit, and containing plural signals in the multi-frame.

CONSTITUTION: Outputs of DS2 stuff circuits 11-14 of a transmitting side are multiplexed by a multiplexing circuit 14 together with a DS1 input of other channel, as second, sixth and seventh channel signals, respectively, and a necessary signals is inserted therein by a C bit parity frame inserting circuit 15 and outputted as a DS3 signal. In this case, the C bit partity frame inserting circuit 15 inserts information related to a stuff processing in the DS3 stuff circuits 11-13 into a C1 bit of a multi-frame. In a receiving side, a necessary signal contained in the received DS3 signal is extracted, and also, demultiplexed. Outputs of second, sixth and seventh channels of a demultiplexing circuit are subjected to destuff processing, based on control information extracted from the C1 bit.


Inventors:
SHIMADA NAOHIRO
Application Number:
JP16209593A
Publication Date:
January 24, 1995
Filing Date:
June 30, 1993
Export Citation:
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Assignee:
NEC CORP
International Classes:
H04J3/00; H04L1/00; (IPC1-7): H04J3/00; H04L1/00
Attorney, Agent or Firm:
Naotaka Ide