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Patent Searching and Data


Title:
The solution to the branching brunch SIMD incore which uses a hardware pointer
Document Type and Number:
Japanese Patent JP6159825
Kind Code:
B2
Inventors:
Reza Yazdani
Application Number:
JP2015555422A
Publication Date:
July 05, 2017
Filing Date:
January 29, 2014
Export Citation:
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Assignee:
ADVANCED MICRO DEVICES INCORPORATED
International Classes:
G06F9/38; G06F9/30; G06F9/32; G06F9/45
Domestic Patent References:
JP2008090744A
JP2003520360A
JP2000509528A
JP2000259579A
Foreign References:
US7287152
US20060242645
Other References:
Wilson W. L. Fung, Ivan Sham, George Yuan, Tor M. Aamodt,Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow,Proceedings of 40th IEEE/ACM International Symposium on Microarchitecture,IEEE,2007年12月 1日,Pages:407-418
Jiayuan Meng, David Tarjan, Kevin Skadron,Dynamic Warp Subdivision for Integrated Branch and Memory Divergence Tolerance,Proceedings of the 37th annual International Symposium on Computer Architecture (ISCA'10),ACM,2010年 6月19日,Pages:235-246
Nicolas Brunie, Sylvain Collange, Gregory Diamos,Simultaneous Branch and Warp Interweaving for Sustained GPU Performance,Proceedings of 39th Annual International Symposium on Computer Architecture,IEEE,2012年 6月 9日,Pages:49-60
Yaohua Wang, et al.,Instruction Shuffle : Achieving MIMD-like Performance on SIMD Architectures,IEEE Computer Architecture Letters,IEEE,2011年12月 6日,Vol:11, No:2,Pages:37-40
Attorney, Agent or Firm:
Yuji Hayakawa
Ryota Sano
Keisuke Murasame